computer-architecture
4 free lessons tagged computer-architecture across Computer Science. Each one is a short sequence of focused steps with narration and a five-question quiz at the end — take them in any order, no signup required.
Why Most Code Is Memory Bound: The Roofline Model
Most real code never approaches a processor's arithmetic peak because it cannot be fed fast enough. The roofline model makes that concrete: plot operational intensity against achievable performance and the binding constraint becomes visible. This lesson covers the model, bandwidth versus latency, and the layout changes that follow.
The Cache Hierarchy and Why Locality Decides Speed
DRAM is roughly two orders of magnitude further away than a register, so processors interpose several levels of cache. This lesson covers measured latencies at each level, cache lines and associativity, the three kinds of miss, and why identical algorithms differ tenfold based on access order alone.
Superscalar and Out-of-Order Execution
Modern cores issue several instructions per cycle and execute them in whatever order their inputs become ready, while still appearing to run the program strictly in order. This lesson covers register renaming, the reorder buffer, the scheduler, and why the instruction window exists at all.
CPU Pipelines: Throughput, Hazards, and Stalls
A processor does not execute one instruction at a time. It overlaps them in a pipeline, which raises throughput without making any single instruction faster. This lesson covers pipeline stages, the three classes of hazard, forwarding, the load-use stall, and why a mispredicted branch is expensive.