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🔌The global semiconductor supply chain

Why chip manufacturing concentrated in a handful of firms and regions, how the lithography chokepoint emerged from compounding R&D, what export-control instruments actually do as a matter of law, what catchup historically required, and the structural risks that follow from the resulting concentration. Six lessons, mechanism-first, with no predictions.

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Lessons in order

  1. 1
    History
    The fab landscape: foundries, IDMs, and fabless firms
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  2. 2
    History
    Lithography as a choke point: DUV, EUV, and the R&D stack
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  3. 3
    History
    Equipment and materials: the secondary chokepoints
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  4. 4
    History
    Export controls as policy: instruments and mechanics
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  5. 5
    History
    Catchup: what closing a node gap actually requires
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  6. 6
    History
    Concentration and risk: single points of failure
    Start