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🔌The global semiconductor supply chain
Why chip manufacturing concentrated in a handful of firms and regions, how the lithography chokepoint emerged from compounding R&D, what export-control instruments actually do as a matter of law, what catchup historically required, and the structural risks that follow from the resulting concentration. Six lessons, mechanism-first, with no predictions.
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Lessons in order
- 1HistoryThe fab landscape: foundries, IDMs, and fabless firmsStart
- 2HistoryLithography as a choke point: DUV, EUV, and the R&D stackStart
- 3HistoryEquipment and materials: the secondary chokepointsStart
- 4HistoryExport controls as policy: instruments and mechanicsStart
- 5HistoryCatchup: what closing a node gap actually requiresStart
- 6HistoryConcentration and risk: single points of failureStart
