Equipment and materials: the secondary chokepoints

A modern logic chip passes through roughly 600–1000 process steps and 50–80 mask layers. Photolithography prints the pattern for each layer; the other 90%+ of the steps do everything else.

The major process categories:

• Etch — selectively remove material exposed by the photoresist stencil. Plasma-based (dry) or chemistry-based (wet).
• Deposition — add a layer of material. Chemical vapor deposition (CVD) for bulk films, physical vapor deposition (PVD) for metals, atomic layer deposition (ALD) for ultra-thin conformal films.
• Ion implantation — accelerate dopant ions (boron, phosphorus, arsenic) into silicon at controlled depth and dose.
• Chemical mechanical planarization (CMP) — polish wafer surfaces flat between layers, because lithography depth-of-focus tolerances are nanometers.
• Cleaning — remove particles and residues between every step. Hundreds of cleans per wafer.
• Metrology and inspection — measure features below the optical resolution limit; detect defects on a 300 mm wafer with sub-nanometer sensitivity.

Each category is its own equipment market, with its own concentration.

Roughly 80% of the global fab equipment market by revenue goes to five firms. Each one specializes — there is little cross-competition between them on their core categories.

Notice the horizontal split: nobody is the leading vendor across all categories. Each firm built decades of process expertise and a deep installed base in its specialty. Switching costs for the fab — both technical (recipe portability) and contractual (service agreements, spares) — keep the boundaries stable.

Etch removes material with selectivity — atoms of layer A but not layer B. As feature sizes shrank, isotropic wet chemistry gave way to directional plasma etch, then to atomic-layer etch (ALE) at the leading edge, which removes one atomic layer per cycle. The transition was driven by the geometry: at 10 nm and below, any sidewall slope is a topology error.

Deposition in modern fabs is dominated by:

• ALD (atomic layer deposition). Self-limiting surface reactions deposit one monolayer per cycle. Required for the conformal high-K dielectric gates that made FinFET possible at 22 nm and stays essential at gate-all-around.
• PECVD / LPCVD. Workhorse film deposition.
• PVD sputtering. Metal layers, especially copper interconnect seeds.

ALD is the clearest example of a process whose adoption was forced by geometry. Before ~22 nm, gate oxides were thin enough that simpler deposition sufficed; below that, the gate had to wrap around a 3D fin or stack of nanosheets, and only ALD could conformally coat the surface.

Photoresist is the photosensitive polymer that records the lithography pattern. Different wavelengths need different chemistries. EUV resist is the hardest case: the photons are higher-energy than DUV, the photon count per exposure is small (shot-noise becomes visible in the resist), and the line edge roughness becomes a noticeable fraction of the feature.

The global EUV photoresist market is supplied by a small group of firms, most of them Japanese:

• JSR Corporation (Japan)
• Tokyo Ohka Kogyo (Japan)
• Shin-Etsu Chemical (Japan)
• Sumitomo Chemical (Japan)
• Fujifilm (Japan)

The concentration is a function of how chemistry-IP-dense the formulation is. Each generation of resist took years of joint development between resist supplier and lithography vendor. The know-how is in compositions and process windows that are not described in patents. A new entrant would face the same multi-year qualification path that the incumbents faced, on a moving target.

Every chip begins as a polished 300 mm single-crystal silicon wafer. Producing one requires:

• A near-perfect single crystal pulled from a melt of 99.9999999% pure silicon by the Czochralski process.
• Slicing into wafers 0.7 mm thick.
• Polishing to surface roughness below 0.5 nm.
• Quality control for defects measured in parts per trillion.

The 300 mm wafer market is supplied by four firms: Shin-Etsu Handotai (Japan), SUMCO (Japan), Siltronic (Germany), and GlobalWafers (Taiwan). Together they cover roughly 90% of global 300 mm wafer supply.

The concentration here is older than the EUV concentration. Wafer production combines metallurgy that took decades to perfect, capital-intensive crystal pullers and polishing lines, and customer-qualification timelines measured in years per process technology. A wafer rejected at incoming inspection can ruin a million-dollar batch at the fab; the relationship is built on multi-decade quality records.

A 300 mm fab consumes hundreds of distinct gases and chemicals at parts-per-billion purity. The categories include:

• Bulk gases — nitrogen, oxygen, argon. Supplied on-site by Air Liquide, Linde, Air Products.
• Specialty etch and deposition gases — silane, ammonia, tungsten hexafluoride, neon, krypton.
• Photolithography support — neon for excimer lasers (one of the world's largest neon uses), ultra-pure water for immersion lithography.
• Wet chemicals — sulfuric acid, hydrogen peroxide, hydrofluoric acid, specialty cleaning formulations.

Neon supply concentrated unusually: a large share historically came from steel-mill byproducts, with a concentration of capacity in Ukraine. The 2022 disruption to Ukrainian neon production triggered a rapid scramble to diversify; this is a case where an apparently obscure input proved to be a single point of failure.

The broader pattern: any input the fab consumes at high purity and high volume has likely consolidated to a small number of qualified suppliers, because qualifying a new one takes years.

At 5 nm and below, features are smaller than the wavelength of visible light. Measuring them requires instruments that operate by other physics:

• Scanning electron microscopy (CD-SEM) — measures feature dimensions on every wafer at multiple points.
• Optical scatterometry — fits diffraction patterns to model the underlying geometry of repeating arrays.
• Atomic force microscopy (AFM) — physical probe contact for sidewall and roughness profiling.
• EUV / e-beam inspection — finds particles and pattern defects below visible-light resolution.

KLA holds the dominant position in process control and yield management software, with optical and e-beam inspection from a small competitive set. The market is concentrated because the value of a defect found early in the process (before $50,000 of wafer cost has been added) is high enough that fabs pay for the best available, and the best available has been refined over decades.

Lithography is the most visible chokepoint, but the broader pattern in chip manufacturing is horizontal concentration with vertical depth.

• Each process category (etch, deposition, metrology, photoresist, wafers, specialty gases) has its own small set of leading suppliers.
• Suppliers in different categories rarely overlap; switching costs at a fab keep the boundaries stable.
• Many suppliers are themselves dependent on single-source sub-suppliers, layered three or four deep.
• The R&D timelines that built each concentration run 10–30 years deep.

When export controls or supply shocks affect the industry, they propagate through this lattice. A restriction on one category (lithography) is the headline; the secondary restrictions, on the equipment, materials, and chemicals that support it, are what determine whether a fab can keep running.

The next lesson moves from describing the industry structure to describing how policy instruments — primarily export controls — have been calibrated to act on it.