The fab landscape: foundries, IDMs, and fabless firms

Chips reach a consumer through one of three corporate structures.

• Fabless — designs chips, owns no fab. Outsources manufacturing to a foundry. Examples: NVIDIA, AMD, Apple's silicon team, Qualcomm, MediaTek, Broadcom.
• Pure-play foundry — runs fabs, designs no chips of its own. Manufactures for fabless clients on a contract basis. Examples: TSMC, GlobalFoundries, SMIC, UMC.
• Integrated Device Manufacturer (IDM) — designs and manufactures its own chips. Sometimes also runs foundry services for outside clients. Examples: Intel, Samsung, SK Hynix, Micron, Texas Instruments.

The three models coexist because they trade off different things: capex risk, design flexibility, IP confidentiality, and yield-curve learning. The rest of this lesson is about which trade-offs pushed which firms toward which structure.

A finished chip touches four to six independent firms before it ships.

The dominant force shaping industry structure is capital expenditure. A leading-edge fab now costs roughly **$20 billion** to build — about ten times what one cost in 2000 and roughly fifty times the cost in 1990. A trailing-edge fab (28 nm and older) runs$1–3 billion. The cost growth is faster than Moore's law in the strict sense, which is why the number of firms operating at the bleeding edge falls each generation.

The math compounds: a fab takes 3–4 years from groundbreaking to ramp, depreciates over 5–7 years, and must run near full utilization to recover the investment. A firm that misses one node — falls behind by 2–3 years on transistor density — loses pricing power on its existing fleet and faces the next $20 B build with weaker cash flow. Two or three missed nodes and exit becomes the rational choice.

Producing logic chips at the leading-edge node (currently 3 nm in volume; 2 nm in early production) is done by three firms: TSMC, Samsung Foundry, and Intel Foundry. A fourth firm, SMIC, produces at 7 nm using DUV multi-patterning — a technique that achieves the geometry without EUV lithography at the cost of more process steps and lower yield.

The trailing-edge picture is more diffuse. At 28 nm and older — which still accounts for roughly 70% of all wafer starts globally — TSMC, GlobalFoundries, UMC, SMIC, Samsung, Tower, Vanguard, and many specialty IDMs compete. Power-management chips, MCUs, automotive logic, RF, and CMOS sensors mostly live here. The leading edge is what attention focuses on; the trailing edge is where most silicon by volume actually ships.

Pure-play foundries (TSMC's model since 1987) and IDMs (Intel's model since the 1970s) make opposite bets.

Intel ran a successful IDM model for decades when its leading-edge process advantage offset the smaller volume it could amortize against. When the process lead narrowed, the model came under strain, which is why Intel split off Intel Foundry Services in the 2020s to court external clients.

A fabless firm pays for designs (engineers, EDA tools, IP licenses) and pays the foundry for wafers. It avoids the $20 B per-fab capex but accepts that its margins are bounded by foundry pricing — the foundry sees the cost structure of every client and prices accordingly.

Fabless works well when (a) the design is complex enough that the IP itself is the bottleneck, (b) the firm can guarantee enough volume to negotiate priority allocation, and (c) it doesn't need exotic process customization. The big wins of the fabless model — NVIDIA, AMD, Apple's silicon team, Qualcomm — share these properties: each ships high-margin chips in volumes large enough that a foundry will dedicate capacity to them, and each can use standard process nodes without bespoke recipes.

The fabless–foundry pair is symbiotic by design: each one's existence makes the other one's business model possible.

Three forces produced today's structure.

• Learning curves. Process yield improves with cumulative wafer volume. A foundry shared across dozens of fabless clients accumulates volume faster than any single IDM can on its own products. Once a foundry pulls ahead on yield at a given node, its cost-per-good-die advantage widens.
• EUV gating. Extreme-ultraviolet lithography became necessary for nodes below ~7 nm. EUV scanners cost ~$200 million each, are made by a single supplier (ASML), and require a fab tooled around their integration. Firms without EUV either stop scaling or use DUV multi-patterning with yield and cost penalties.
• Compound capex. Each node's fab is more expensive than the last. Firms that miss a node fall behind on both volume and cost-per-good-die, which compounds across generations.

None of these forces require any policy choice or geopolitical event. The structure that emerged is what those three forces compounded to over four decades.

Three structural consequences follow from a leading edge run by three firms:

• Single points of failure. A natural disaster, labor disruption, or regulatory shock at one fab disproportionately affects global supply at that node.
• Negotiation asymmetry. A fabless client with one realistic supplier for its node has limited pricing leverage and limited recourse if allocation is cut.
• Strategic visibility. A foundry serving most of the leading edge sees the demand pipeline of competing fabless clients before any of them ships product, which has informational consequences regardless of how strict the client-isolation policies are.

These are observations about industry structure, not predictions about specific outcomes. The lessons that follow examine the chokepoints in lithography, equipment, and materials; the policy mechanics of export controls; and the math of what catchup actually requires.