semiconductors
16 free lessons tagged semiconductors across History, Science. Each one is a short sequence of focused steps with narration and a five-question quiz at the end — take them in any order, no signup required.
Concentration and resilience: what it takes to de-risk a chip supply chain
Mapping the single points of failure in semiconductor production, why building fabs elsewhere is necessary but nowhere near sufficient, the real toolkit of resilience strategies with their costs, and a transferable method for analyzing any concentrated supply chain.
Export controls: how supply-chain chokepoints become policy
The legal machinery of technology export controls, explained structurally: control lists and licensing, the Entity List, the Foreign Direct Product rule's extraterritorial reach, node thresholds, multilateral coordination, and the enforcement limits every control system carries.
Lithography: the machine that prints the modern world
How chips are printed with light, why extreme ultraviolet lithography took three decades and a continent-wide supplier tree to build, and how one company's machines became the deepest technical moat, and sharpest policy lever, in the semiconductor chain.
The foundry model: how chipmaking split into designers and fabs
Why the semiconductor industry separated into fabless designers and a handful of contract manufacturers, the capital economics that drive relentless concentration, and the map of who actually makes the world's chips.
Concentration and risk: single points of failure
The geographic and corporate concentration of the chip supply chain expressed as engineering risk — single points of failure, the cost of redundancy, hedging strategies, and the customer-side concentration that mirrors the supply side. Structural analysis, not prediction.
Catchup: what closing a node gap actually requires
The structural ingredients required to move a national or corporate semiconductor capability up the node ladder — capital, equipment access, process know-how, and talent — and the historical examples (Korea, Taiwan) of how earlier catchup campaigns played out.
Export controls as policy: instruments and mechanics
How the US, Dutch, and Japanese export-control regimes for advanced semiconductors actually function — the legal instruments, the parameter thresholds in published regulations, the extraterritorial Foreign Direct Product Rule, and the licensing-and-enforcement mechanics.
Equipment and materials: the secondary chokepoints
Beyond lithography, a fab depends on etch, deposition, implantation, metrology, photoresist, wafers, and specialty gases. Each of these markets concentrated independently, and most show the same compounding-R&D pattern as lithography at smaller scale.
Lithography as a choke point: DUV, EUV, and the R&D stack
Why chip resolution is bounded by light wavelength, how the industry moved from 193 nm DUV to 13.5 nm EUV, and what makes lithography one of the most concentrated single-vendor markets in modern manufacturing.
The fab landscape: foundries, IDMs, and fabless firms
The three business models in chip manufacturing — fabless designer, pure-play foundry, integrated device manufacturer — and the capex, yield, and learning-curve forces that drove the leading edge into a small handful of firms.
Scaling and the end of Moore's law
Why Dennard scaling died in 2005, how the industry kept Moore's law alive through FinFET, gate-all-around, and chiplet packaging, and why modern chips look like zoos of specialized accelerators sitting half-dark. The constraints that produced the modern SoC and the frontiers that come next.
Chip fabrication: wafer to working device
How a near-perfect silicon ingot becomes a billion-transistor chip. The 600-step fab cycle, photolithography down to 13.5 nm EUV (vaporized tin droplets at 220,000 °C), ion implantation for doping, the truth behind '5 nm' node naming, and the chokepoint-heavy global supply chain.
CMOS logic: from transistors to chips
How pairing NMOS with PMOS creates digital gates that draw zero steady current. The CMOS inverter, NAND/NOR construction, the static-vs-dynamic power split that DVFS exploits, propagation delay and fan-out, and the scaling path from one inverter to a 25-billion-transistor SoC.
Transistors: BJTs and MOSFETs
The two transistor families that built modern electronics. BJTs as current-controlled amplifiers, MOSFETs as voltage-controlled switches with a capacitor for a gate, the three operating regions of each, and the four reasons MOSFETs ended up running every digital chip.
Diodes: the simplest semiconductor device
From a single PN junction to the four-diode bridge in every wall adapter. The IV curve, rectification, Zener voltage references, fast Schottky diodes for switching supplies, LEDs and photodiodes turning current to light and back, and the five failure modes that bite real designs.
Semiconductor basics: bands, doping, and the PN junction
What makes silicon work where diamond won't, why doping turns an insulator into a tunable conductor, and how slapping p-type silicon next to n-type creates the depletion region that becomes a diode. The physics every chip is built on.