Catchup: what closing a node gap actually requires

Moving from one process node to the next — whether by an existing firm climbing the ladder or by a new entrant trying to reach a competitive node — requires four ingredients in compounding combination.

• Capital — multi-billion-dollar fab construction, plus operating losses during ramp.
• Equipment access — lithography scanners, etch tools, deposition systems, metrology, and the maintenance contracts that keep them running.
• Process know-how — recipes, integration, yield-learning data, and design-for-manufacturing rules that exist only in the form of trained engineers and accumulated process logs.
• Talent — process engineers, physicists, chemists, and managers with direct experience of the previous node, in a quantity sufficient to staff multiple fabs.

Missing any one ingredient bounds the others. A firm with unlimited capital and no process know-how will spend it without closing the gap. A firm with the know-how but no access to leading-edge lithography will be unable to print the geometry, however efficient its design. The structural pattern this lesson examines is how each ingredient has historically been assembled, and what happens when one is removed.

Two examples of national catchup are sufficiently documented to ground the discussion.

Korea (Samsung, Hynix), ~1983–2010s. Korean firms entered DRAM in the early 1980s with state support and foreign licensing. Samsung achieved process parity with the leading Japanese DRAM producers by the late 1990s and overtook them in the 2000s. The campaign required ~25 years of sustained investment, multiple government industrial-policy cycles, deep technology licensing, and a willingness to absorb large operating losses during downturns.

Taiwan (TSMC), 1987 onward. TSMC was founded with state participation in 1987 with a single explicit thesis: pure-play foundry as a business model. It took TSMC roughly two decades to reach process parity with the leading IDMs and then to surpass Intel on logic process by the late 2010s. The campaign benefited from the diaspora of engineers educated abroad returning to Taiwan and from government coordination on infrastructure and education.

The shared features: 20+ year timelines, sustained state involvement (not always majority ownership, but always strategic coordination), and the build-up of a domestic engineering base around the firms.

A new fab at the leading edge costs ~$20 billion to build. The fab generates losses during ramp because:

• Yields start low (often 10–30% at first wafers) and climb over 1–3 years to mature levels (~80% or higher).
• Depreciation begins on day one even as good-die output ramps slowly.
• Customer qualifications take 6–18 months per major product.

The cumulative operating loss during ramp can run several billion dollars per fab. A firm without deep balance-sheet support or sustained state backing typically cannot absorb this without external financing on terms that compromise the catchup goal (e.g., diluting equity, taking on debt that constrains future investment).

This is the simplest reason catchup historically required state coordination: only states (or vertically integrated technology giants with adjacent profitable businesses) have the time horizon and risk tolerance to fund decade-long unprofitable campaigns. The mathematics of the capex-and-yield curve makes that conclusion structural, independent of any political view.

Of the four ingredients, equipment access is the most binary: a fab either has the scanner or it does not.

For leading-edge logic today, the binding equipment constraints include:

• EUV lithography — required for nodes below ~7 nm at acceptable cost and yield. Sole vendor (ASML). Currently subject to Dutch and (for some configurations) US export controls to specific destinations.
• Advanced DUV immersion — required for 7 nm without EUV, via multi-patterning. Same vendor.
• High-energy ion implanters — required for shallow junctions at the leading edge.
• Atomic-layer deposition systems — required for conformal high-K dielectrics on 3D transistor geometries.
• Advanced metrology — required for in-line process control at sub-10 nm features.

Without access to a category of equipment, a firm either substitutes (e.g., DUV multi-patterning for EUV, with cost and yield penalties), develops it domestically (a multi-decade R&D campaign), or accepts staying at a prior node. Each of those is a structural choice with quantifiable trade-offs, not a hypothetical.

A fab's process recipe is not a printable document. It is the integration of thousands of parameters — temperatures, gas flows, exposure doses, anneal times, sequence orderings — refined over millions of wafers and tens of thousands of engineering hours. The recipe lives partly in process control software, partly in engineering notebooks, and significantly in the trained intuition of the engineers running the line.

The structural consequences:

• Process porting is hard. Moving a recipe from one fab to another, even with the same equipment, requires re-tuning and re-qualification that takes 6–24 months per process generation.
• Reverse engineering doesn't work. Looking at a finished chip tells you the layout, but not the recipe that produced it. The information loss between chip and process is severe.
• Talent moves matter disproportionately. Hiring 50 senior process engineers from a leading fab can compress a multi-year qualification campaign in ways that no amount of capex or equipment can.

This is why historical catchup campaigns leaned heavily on technology transfer agreements, joint ventures, and the recruitment of diaspora engineers. It is also why patents alone do not protect process-know-how positions.

When process-level catchup is constrained, design-level innovation can partially compensate.

• Architectural improvement. A better design at an older node can outperform a worse design at a newer node on specific workloads. This is bounded — process-level density and energy efficiency advantages accumulate generation over generation — but the bound is not at zero.
• Advanced packaging. Chiplets, 2.5D and 3D integration, silicon interposers, and through-silicon vias let a designer assemble a finished system from dies of different nodes. A logic die on the leading edge, a memory die on the prior node, and an I/O die on a mature node can be packaged together. Packaging can compensate for one node's lag if the binding bottleneck is in a specific functional block.
• Workload-specific accelerators. A design specialized for one workload (e.g., a particular neural network architecture) can match a more general design at a newer node for that workload while trailing on others.

The limit of design-level workarounds is the eventual return of the process advantage: a competitor that has both the better design and the better process retains a structural lead. But the workarounds extend the useful life of a trailing-edge position by years, which is itself an outcome with strategic value.

SMIC produces logic at 7 nm using 193 nm DUV immersion lithography with multi-patterning, without EUV. This demonstrates that 7 nm is not a hard physical wall without EUV; it is a cost and yield wall.

The trade-offs at 7 nm without EUV:

• More exposure passes per critical layer. A layer that takes one EUV exposure may take three or four DUV exposures with multi-patterning (SAQP, LELELE, etc.).
• More masks per layer. Each pass requires its own mask, multiplying mask cost and design complexity.
• Lower yield per layer. Each pass adds defect opportunities; cumulative defects grow with pass count.
• Lower throughput. Wafer-per-hour rates fall because of the additional exposure time.
• Higher cost per good die. All of the above combine to raise the cost of a finished die well above what EUV achieves at the same geometry.

The combination means 7 nm via DUV multi-patterning is technically feasible, but it serves a different position in the cost-performance frontier than EUV-printed 7 nm. Whether that position is commercially viable depends on the demand curve — what fraction of buyers will pay a premium for the geometry over what their workload requires, and at what volume.

A simplified model of the catchup gap:

$\text{gap}(t) = \text{gap}(0) - r_{\text{catchup}} \cdot t + r_{\text{lead}} \cdot t$

where $r_{\text{catchup}}$ is the rate at which the catching firm closes the gap, and $r_{\text{lead}}$ is the rate at which the leading firm extends it. The catching firm closes the gap only if $r_{\text{catchup}} > r_{\text{lead}}$, sustained.

The structural conditions for $r_{\text{catchup}} > r_{\text{lead}}$ historically include:

• Faster talent recruitment than the leader's organic growth.
• Higher capex tolerance than the leader's profitable reinvestment.
• Equipment access on terms close to the leader's.
• A focused product strategy that avoids the leader's strongest segments while the gap closes.

The Korean and Taiwanese catchup campaigns met these conditions over multi-decade horizons. Whether any current campaign meets them is an empirical question whose answer depends on policy, market conditions, and corporate choices that this lesson cannot anticipate. The structural framework — the four ingredients, their interaction, and the historical timescales — is the same. The values to plug into it change.

The final lesson in this cursus turns from the mechanics of catchup to the structural risks created by current concentration: single points of failure, the informational and negotiation asymmetries that follow from concentration, and the consequences without prediction.