vlsi

Why Dennard scaling died in 2005, how the industry kept Moore's law alive through FinFET, gate-all-around, and chiplet packaging, and why modern chips look like zoos of specialized accelerators sitting half-dark. The constraints that produced the modern SoC and the frontiers that come next.

How pairing NMOS with PMOS creates digital gates that draw zero steady current. The CMOS inverter, NAND/NOR construction, the static-vs-dynamic power split that DVFS exploits, propagation delay and fan-out, and the scaling path from one inverter to a 25-billion-transistor SoC.