CMOS logic: from transistors to chips

NMOS turns on when its gate is high. PMOS turns on when its gate is low. Stack one of each on a single input and exactly one of them is on at any time — never both, never neither (except for a sliver of nanoseconds during switching).

That "never both" is the whole point. In a non-CMOS gate, a steady DC path always exists from supply to ground through the transistors; current flows continuously and energy dumps as heat. In CMOS, when the input is settled (high or low), the path is broken at one transistor or the other. The gate draws no steady current.

This is the foundation of every digital chip from 1985 to today. The next four steps walk through the simplest CMOS gate, how every other gate is built from the same building blocks, then what "no steady current" really costs once you actually start switching.

Two transistors. PMOS on top with source at $V_{DD}$ (the supply). NMOS on bottom with source at ground. Both gates tied to the input. Both drains tied to the output.

In either steady state, one transistor is fully off — so there's no path from $V_{DD}$ to ground. Steady-state current: ideally zero (in practice, a tiny leakage through the off transistor).

The inverter's output is the opposite of its input. Combined with a NAND or NOR (either one is functionally complete), it's all you need to build every digital function — adders, multipliers, memories, processors.

Input drives both gates. PMOS pulls up when input is low; NMOS pulls down when input is high.

To build a NAND or NOR gate, the same recipe applies: a pull-up network of PMOS on top, a pull-down network of NMOS on bottom, with the two networks being topological duals of each other.

• 2-input NAND: pull-down is two NMOS in series (both inputs high → output pulled to 0). Pull-up is two PMOS in parallel (either input low → output pulled to $V_{DD}$).
• 2-input NOR: pull-down is two NMOS in parallel (either input high → output pulled to 0). Pull-up is two PMOS in series (both inputs low → output pulled to $V_{DD}$).

At any input combination, exactly one network conducts and the other is broken — same "no steady DC path" property as the inverter. More complex gates (XOR, AOI, MUX) follow the same dual-network pattern with more transistors. A static CMOS gate of $n$ inputs uses $2n$ transistors.

Add up the steady-state current of a CMOS gate at idle: essentially zero. That's what makes CMOS scale to a billion transistors on one die.

The leakage isn't exactly zero, of course:

• Subthreshold leakage — even when $V_{GS} < V_T$, a tiny current still flows. It rises exponentially as the threshold drops.
• Gate-oxide tunneling — with oxides under 2 nm thick, electrons quantum-tunnel through the gate oxide. A real problem from the 65 nm node onward.
• Junction leakage — reverse-biased source/drain junctions leak microamps per device.

At the 5 nm node, leakage can account for 30–40% of total chip power at idle. This is why modern chips power-gate entire blocks (cut $V_{DD}$ to areas not in use) and why the leakage-vs-performance tradeoff drives threshold voltage choices.

Every output transition charges or discharges the load capacitance $C_L$ through the supply rail:

$P_{dyn} = \alpha \cdot C_L \cdot V_{DD}^2 \cdot f$

where $\alpha$ is the activity factor (fraction of cycles where the node toggles), $C_L$ is the load capacitance, and $f$ is the clock frequency. Two consequences:

• $V_{DD}^2$ scaling: cut the supply from 1.2 V to 0.8 V and dynamic power drops by more than half. Every modern chip aggressively scales $V_{DD}$ with frequency. DVFS — dynamic voltage and frequency scaling — is built on this.
• Activity matters: gates that toggle every cycle dominate power. Clock distribution networks consume 20–40% of total chip power because the clock toggles every cycle (the highest possible $\alpha$).

Total power: $P_{total} = P_{dyn} + P_{static}$. Modern chips balance both.

Each gate has a propagation delay — the time from input change to output settling. Two pieces:

• Intrinsic delay: how fast the gate charges/discharges its own internal capacitance.
• Load delay: how fast it can drive its load $C_L$. Bigger load → more delay.

The number of gate inputs a single gate output drives is the fan-out. Each input adds gate capacitance to the load. Fan-out of 4 (FO4) is the standard reference design point — a gate driving four copies of itself. Most modern logic targets each gate to drive ~3–6 loads.

Drive too much load and delay grows. The fix is buffer chains: insert progressively larger inverters to amplify drive strength. The classic result: an exponential-stage chain with optimal taper factor $e \approx 2.7$ minimizes total delay. This shows up everywhere in clock distribution and signal repeaters.

Three scaling steps separate one CMOS inverter from a modern system-on-chip:

• Standard cells: a library of pre-laid-out gates (INV, NAND2, NOR2, DFF, AOI21, MUX, ...) with characterized timing and power. Synthesis tools choose which to use; place-and-route tools wire them together.
• Functional blocks: ALUs, register files, caches, multipliers — each built from thousands to millions of standard cells via RTL synthesis.
• The SoC: CPU cores, GPUs, NPUs, memory controllers, PHYs, sensors. Tens of billions of transistors orchestrated by a clock tree, a power grid, and a thermal envelope.

The CMOS inverter is still the atom of all of it. An Apple M3 has roughly 25 billion transistors; every one is an NMOS or PMOS, and almost every gate uses the same pull-up / pull-down structure described two steps above. Scaling didn't change the principle — it changed the scale.