Scaling and the end of Moore's law

Two related observations shaped the semiconductor industry from 1965 onward.

Moore's law (Gordon Moore, 1965): transistor count per chip doubles roughly every two years. This was an economic observation — what makes chips cheaper to design and manufacture — not a physical law.

Dennard scaling (Robert Dennard, 1974): when you shrink transistor dimensions by a factor $k$, you also shrink voltage by $k$, so:

• Area drops by $k^2$.
• Capacitance drops by $k$.
• Delay drops by $k$ (faster).
• Power per transistor drops by $k^2$ (cooler).
• Power density stays constant.

The last point was the magic. You could shrink the transistor and keep total chip power constant and pack more transistors and run them faster. Every two years, free performance. For 30 years this held.

For three decades the gains stacked beautifully:

• 1971: Intel 4004 — 2,300 transistors, 740 kHz.
• 1985: Intel 80386 — 275,000 transistors, 16 MHz.
• 2000: Pentium 4 — 42 million transistors, 1.5 GHz.
• 2010: Intel Westmere — 1.17 billion transistors, 3.3 GHz.
• 2024: Apple M4 Max — ~28 billion transistors, 4.5 GHz.

Transistor count: doubled every ~2 years. Clock speed: doubled every ~3 years. Power per transistor: dropped by ~30% per generation. Software didn't have to do anything — the same code ran faster every year.

But zoom in on the clock-speed numbers. Pentium 4 hit 3.8 GHz in 2004. Today's flagships are 5 GHz. Twenty years for 30% more clock. Something broke in the early 2000s. The next step is what.

Dennard scaling died around 2005 for a physical reason: leakage current stopped scaling.

The rule said: shrink transistor by $k$, drop voltage by $k$, drop threshold by $k$, density doubles, power stays constant. But:

• Drop threshold $V_T$ too far and subthreshold leakage explodes (exponential in $V_T$).
• Drop oxide thickness too far and gate-oxide tunneling leakage shows up.
• Drop supply $V_{DD}$ too far and circuits lose noise margin.

The industry stopped scaling voltage around $V_{DD} = 1.0$ V (2005-ish). With voltage fixed and transistor density still doubling, power density rises every generation. Worse — leakage now contributes ~30% of total power at idle.

Moore's law (transistor count) keeps going. Dennard scaling (free performance + constant power) doesn't. Everything else in this lesson is consequences.

Each generation rebuilt the transistor's geometry to keep scaling working under new constraints.

To keep scaling working under leakage pressure, the geometry of the transistor itself had to change.

Planar MOSFET (until ~2010): gate sits flat on top of a flat channel. As channel length shrinks below ~20 nm, the drain field couples into the channel and leakage explodes — the gate loses control.

FinFET (Intel 22 nm, 2011): stand the channel up as a thin fin and wrap the gate around three sides. Better electrostatic control; the gate dominates again. Enabled scaling from 22 nm down to 3 nm.

Gate-all-around (GAA, Samsung 3 nm, 2022): stack horizontal silicon nanosheets and wrap the gate completely around each. Maximum gate control, smaller footprint, drive strength tunable by nanosheet count. Will carry CMOS to ~2 nm and below.

Complementary FET (CFET, post-2027): stack PMOS directly over NMOS in 3D. Roughly halves CMOS footprint. Currently a research roadmap.

With power density rising every generation, a quiet thing happened: you can't power-on the whole chip at once anymore.

Dark silicon is the fraction of a chip that must remain inactive at any moment to stay within the thermal budget. By the 14 nm node, estimates ran from 21% to 50% dark silicon for general-purpose logic. At 5 nm and below, half the die may be dark on a typical workload.

The industry response has been specialization:

• Embed many different accelerators (NPU, ISP, video encoder, crypto engine) instead of more identical CPU cores.
• Power-gate aggressively — wake only the block needed for the task at hand.
• Use heterogeneous cores (Apple's performance + efficiency cores; Intel's P + E cores).

This is why every modern SoC looks like a zoo: dozens of specialized blocks, each idle most of the time, each ready for one specific workload. Dark silicon is the constraint that produced the modern SoC.

Monolithic single-die designs hit two walls: yield (defect rate × area) and reticle limit (max die size in one lithography exposure, ~858 mm² for EUV).

Chiplets break a design into multiple smaller dies — each independently fabricated, then connected on an interposer or package substrate. AMD's Ryzen and Epyc CPUs, Apple's M Ultra series, and NVIDIA's Blackwell GPUs are all chiplet-based.

The payoff:

• Better yield: smaller dies have fewer defects per die.
• Mix nodes: build the compute die on expensive 3 nm; build the memory controller on cheap 7 nm. Match cost to need.
• Reuse: ship the same I/O die across multiple SKUs.

Key packaging tech: TSMC's CoWoS (chip-on-wafer-on-substrate) for the high-end, Intel's Foveros for 3D-stacked logic, and silicon bridges (EMIB) for dense die-to-die links. Inter-chiplet bandwidth has gone from ~30 GB/s (2017) to multi-TB/s (2024).

With FinFET → GAA → CFET, transistor scaling has maybe a decade left at the leading edge. Three frontiers are active:

• 3D stacking — stack logic dies vertically with through-silicon vias (TSVs) and hybrid bonding. AMD's V-Cache (vertical SRAM on top of a CPU) is the first mass-shipped example. Stacking logic-on-logic is harder (thermal, EDA) but feasible.
• New materials — replace silicon channels with germanium or 2D materials (MoS₂, WSe₂) for higher mobility. SiC and GaN are already standard in power (chargers, EVs) and RF. Mainstream digital is harder.
• Beyond CMOS — spintronics, tunneling transistors, ferroelectric FETs, optical interconnect. Each is a research bet that may or may not break out of the lab.

Moore's law as economic doubling is sputtering — cost per transistor barely fell from 16 nm to 5 nm. Density still grows. The next decade of progress comes from architectural and packaging cleverness, not raw shrink. The era of "new node, free performance" is over.