Chip fabrication: wafer to working device

Every chip starts as a near-perfect single-crystal silicon ingot. The recipe (Czochralski process):

• Melt ultra-pure (99.9999999%) polysilicon in a quartz crucible at 1414 °C.
• Dip a small seed crystal into the melt and slowly pull it up while rotating.
• The crystal grows beneath the seed as silicon freezes onto it. One ingot ends up 30+ cm in diameter and over a meter long.

Slice the ingot into wafers about 0.7 mm thick, polish to mirror smoothness (variations under 0.5 nm), and you have the substrate for hundreds of chips.

The wafer is the single most boring-looking part of a chip and the result of decades of metallurgy. Every defect on it — every misplaced atom — directly becomes a yield problem 1000 process steps later. The ingot business is dominated by Shin-Etsu, SUMCO, and Siltronic; cleanrooms downstream care about parts per trillion contamination.

A chip isn't manufactured in one shot — it's built layer by layer. The fab cycle is a repeating four-step pattern executed 50–100+ times per chip:

• Photolithography — paint photoresist on the wafer; expose it through a mask; develop it. Now you have a stencil of where the next operation should happen.
• Etch — remove material from unmasked areas. Either wet chemistry or directional plasma.
• Deposit — add a layer of material (silicon dioxide, polysilicon, copper, high-K dielectric). Methods include CVD, PVD, ALD.
• Dope (sometimes) — implant phosphorus or boron ions where the stencil exposes silicon.

Then strip the resist and start over for the next layer. A 5 nm chip has ~80 lithography layers and 600+ total process steps. Total time from raw wafer to packaged chip: 8–12 weeks.

Four major steps per layer; modern chips repeat the loop ~80 times.

The mask is a quartz plate with a chrome pattern — the blueprint of one layer of the chip. Photolithography prints that pattern onto the wafer at ~4× reduction.

The key constraint is wavelength. The smallest feature you can resolve is set by the Rayleigh criterion:

$\text{CD} = k_1 \cdot \frac{\lambda}{\text{NA}}$

where CD is the critical dimension, $\lambda$ is the wavelength, NA is the numerical aperture of the lens, and $k_1$ is a process constant (~0.25 with all the tricks). For decades the industry rode this equation downward:

• 248 nm (KrF excimer laser): 250 nm features.
• 193 nm (ArF): 90 nm and below with immersion lithography (water under the lens raises NA).
• 13.5 nm (extreme ultraviolet): 5 nm features and beyond.

No conventional light source produces 13.5 nm photons. The next step explains how EUV does it.

To make 13.5 nm light, ASML's EUV machine — the most complex machine ever sold commercially — does this 50,000 times per second:

• A 30 μm tin droplet falls through a vacuum chamber.
• A first laser pulse flattens the droplet into a pancake.
• A second high-power CO₂ laser pulse vaporizes the pancake into plasma at 220,000 °C.
• The plasma emits a flash of 13.5 nm EUV light.

EUV is absorbed by everything — air, glass, even most metals. So:

• The entire optical path is held in vacuum.
• Lenses are impossible. Light bounces off 10+ multilayer mirrors with 99% reflectivity each. Total photon throughput: ~1%.
• The mask is also reflective, not transmissive.

ASML in the Netherlands is the only company that makes EUV scanners. Each costs ~$200 million and weighs 180 tons. There are fewer than 200 deployed globally.

Modern doping is ion implantation: phosphorus or boron ions accelerated to 10–200 keV and shot into the wafer through the stencil. Depth depends on energy; dose on beam current and time. Anneal afterward (rapid thermal processing, ~1000 °C for seconds) to repair lattice damage and activate the dopants.

Why not gas-phase diffusion (the older method)? Implantation is digitally controllable. You set dose and energy on a knob; diffusion depends on time, temperature, and uniformity of gas flow.

Dopant placement is the most precise step in the whole fab:

• Source/drain implants must be aligned with the gate edge to within a nanometer (no overlap, no gap).
• Channel doping sets threshold voltage to within 10–50 mV across a billion transistors.
• Modern halo and pocket implants control short-channel effects at <10 nm gate lengths.

Get the doping wrong and the chip works at 25 °C and fails at 85 °C.

The 'node name' — 28 nm, 10 nm, 5 nm, 3 nm — used to mean the gate length of the smallest transistor. Around the 20 nm node (~2014) that stopped being true. Today it's a marketing label that compares roughly to a competitor's offering, not a physical measurement.

The useful metric is transistor density (transistors per mm²). Density has doubled roughly every two years for decades — Moore's law as actually measured — even as the 'nm' label became less and less physical.

Making a chip touches more companies than building a car. The 2020s supply chain has clear pinch points:

• Design tools — Synopsys and Cadence together account for ~70% of EDA. No fabless company designs without them.
• IP cores — Arm licenses CPU architectures used in ~95% of mobile and embedded chips. RISC-V is the open-source challenger.
• Foundries — TSMC fabricates >50% of the world's logic chips and >90% of leading-edge nodes. Samsung is a distant second; Intel is fighting to re-enter.
• Lithography — ASML (Netherlands) is the sole EUV vendor. Nikon and Canon make DUV.
• Equipment — Applied Materials, Lam Research, Tokyo Electron, KLA. Each dominates specific process steps (deposition, etch, metrology).
• Silicon wafers — Shin-Etsu, SUMCO, Siltronic supply most 300 mm output.
• Specialty chemicals and gases — Air Liquide, Linde, JSR, Tokyo Ohka.

No single country has the whole stack. Export controls on any one link ripple across the entire industry — which is exactly what 2022's US-China chip restrictions tested.