The foundry model: how chipmaking split into designers and fabs

Chips are in everything: cars, phones, missiles, thermostats, data centers. Yet the capability to manufacture the most advanced ones is held by fewer companies than you can count on one hand, operating in fewer places than you can count on the other.

A rough sketch of the concentration, at the leading edge of logic chips:

• One contract manufacturer produces on the order of 90% of the most advanced logic chips (below the 7-nanometer class).
• One equipment maker supplies 100% of the lithography machines required to make them.
• A handful of firms, mostly in one or two countries each, control the critical chemicals, wafers, optics, and packaging.

This lesson path treats that concentration as a structure to be explained, not a scandal or a triumph. The questions are mechanical: why did the industry split into designers and manufacturers? Why does manufacturing keep collapsing toward one or two players? Why can a single machine become a national policy instrument? And what does resilience actually require? The answers generalize far beyond chips, to any industry where scale economics compound for decades.

A fab (fabrication plant) turns blank silicon wafers into finished chips through hundreds of process steps: growing and depositing layers of material, printing patterns onto them with light (lithography), etching material away, implanting atoms to change electrical behavior, and inspecting everything at nanometer scale, repeated layer upon layer for up to three months per wafer.

The defining economic facts:

• A leading-edge fab costs on the order of $20-30+ billion to build and equip, and it must be refilled with new equipment each process generation.
• It only pays for itself when run flat out, around the clock, for years. Utilization is everything; an idle fab burns money at a staggering rate.
• Yield (the fraction of chips that work) starts low on every new process and climbs only through painful, experience-driven iteration. Yield learning is the core trade secret of the industry.

These three facts, extreme fixed costs, utilization pressure, and experience-based yield, are the physics behind everything else in this path. An industry with this cost structure wants to concentrate: whoever has the most volume learns fastest, fills their fab best, and can afford the next, even more expensive generation.

Through the 1970s and 80s, chip companies were integrated device manufacturers (IDMs): they designed chips and owned the fabs that made them. As fab costs exploded, that bundle broke.

The foundry model, pioneered by TSMC at its founding in 1987, made a then-radical promise: we will only manufacture, and we will never design chips that compete with our customers. That single commitment unlocked the other half of the industry: fabless companies, which design chips and own no factories at all.

The division of labor that resulted:

• Fabless designers (think of the firms behind GPUs, phone processors, AI accelerators) carry no fab risk and iterate on design, where their advantage lies.
• Pure-play foundries aggregate manufacturing volume from hundreds of fabless customers, achieving the utilization and yield learning no single designer could justify alone.
• IDMs persist where design and process are still deeply intertwined, memory chips, and some logic, with the leading-edge logic IDMs increasingly opening their fabs to outside customers too.

Note the flywheel: every new fabless company adds volume to the foundries, which improves foundry economics, which makes going fabless more attractive. The foundry model did not just serve concentration; it manufactured it.

The modern semiconductor value chain: design tools and IP feed fabless designers; foundries manufacture using equipment and materials from specialized suppliers; assembly and packaging finish the product. Each box hides its own concentration story.

In 2001, roughly two dozen companies could manufacture at the then-leading edge. Each subsequent process generation, the club shrank: the next node always costs more to develop, demands more volume to pay off, and punishes yield mistakes harder. Firms faced a recurring decision, invest billions to stay at the edge, or step off the treadmill and serve mature nodes profitably. One by one, nearly all stepped off.

By the 2020s, exactly three firms still manufactured leading-edge logic: TSMC (Taiwan), Samsung (South Korea), and Intel (United States), and their positions are not equal. TSMC's share of the most advanced logic production is around 90%, reflecting a compounding advantage: highest volume, fastest yield learning, deepest customer relationships, and first claim on scarce equipment.

Two structural notes keep the picture honest:

• The leading edge is not the whole industry. Most chips by unit count (cars, appliances, power management) use mature processes made by many firms in many countries. Concentration is extreme specifically where transistors are smallest.
• Concentration here is not primarily a policy failure or conspiracy; it is the equilibrium of an industry where fixed costs double roughly every generation and experience compounds. Any effort to reshape it (next lessons) works against that gradient.

The economics become concrete with one back-of-envelope calculation. Stylized numbers for a leading-edge process:

Fab cost (build + equip)   : $25,000,000,000
Useful leading-edge life   : ~5 years before next-gen refit
Capacity                   : ~50,000 wafer starts/month

Capital cost per wafer     : $25B / (5y x 12mo x 50,000)
                           = ~$8,300 per wafer  (capital alone)

A leading-edge wafer sells for roughly $15,000-20,000.
One wafer yields ~60 large AI-accelerator dies or ~600 phone chips.

Now cut utilization to 50%:
Capital cost per wafer     : ~$16,600  -> the fab loses money
                              before paying for labor or materials.

Every structural fact of the industry falls out of this arithmetic: why foundries pool demand from hundreds of customers (utilization), why the leading edge supports so few players (the $25B ante), why customers prepay and sign multi-year commitments (the fab needs certainty before pouring concrete), and why a demand shock (a phone slump, an AI boom) whipsaws the entire chain. The gotcha for intuition: chips are cheap; chip capacity is brutally expensive. The marginal chip costs little; the standing ability to make chips is what the world's most valuable manufacturing firms actually sell.

Foundries get the headlines, but they assemble their capability from suppliers that are often more concentrated than the foundries themselves:

Two lessons hide in the table. First, the chokepoint is rarely where you first look: replicating a foundry without its supplier tree replicates nothing, a fact central to both export-control design (lesson 3) and resilience plans (lesson 4). Second, concentration has different causes at different layers: lithography's is R&D depth (next lesson), materials' is decades of process-purity know-how, packaging's is labor economics plus proximity to fabs. There is no single lever that de-concentrates a chain like this.

Compress the lesson into four structural rules; they recur throughout this path:

1. Fixed costs sort industries. When the ante doubles every generation, the number of players halves until only volume leaders remain. Chip manufacturing is the extreme case, not an exception to normal economics.
2. Experience is a moat that compounds. Yield learning rewards whoever runs the most wafers, so leadership converts into more leadership. Catching up requires absorbing losses for years while the leader keeps moving.
3. Specialization creates hidden single points of failure. The efficient global arrangement, each layer perfected by one or two specialists, is also the fragile one. Efficiency and resilience trade off directly.
4. The map of capability is not the map of revenue. Small firms (a mask-blank maker, an optics supplier) can hold veto power over trillion-dollar downstream industries.

With the structure in place, the path drills into its three most consequential features: the lithography monopoly, the deepest technical moat in industrial history and the reason one machine ships with its own diplomatic significance (next lesson); export controls, the legal machinery that turns supplier concentration into policy leverage (lesson 3); and the resilience question, what it would actually take to make this chain less brittle (lesson 4).